[PATCH] D151178: [RISCV][NFC] Simplify code.
Jianjian Guan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 22 23:37:41 PDT 2023
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc6d3347e1376: [RISCV][NFC] Simplify code. (authored by jacquesguan).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D151178/new/
https://reviews.llvm.org/D151178
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -264,25 +264,19 @@
setLibcallName(RTLIB::MULO_I64, nullptr);
}
- if (!Subtarget.hasStdExtM() && !Subtarget.hasStdExtZmmul()) {
+ if (!Subtarget.hasStdExtM() && !Subtarget.hasStdExtZmmul())
setOperationAction({ISD::MUL, ISD::MULHS, ISD::MULHU}, XLenVT, Expand);
- } else {
- if (Subtarget.is64Bit()) {
- setOperationAction(ISD::MUL, {MVT::i32, MVT::i128}, Custom);
- } else {
- setOperationAction(ISD::MUL, MVT::i64, Custom);
- }
- }
+ else if (Subtarget.is64Bit())
+ setOperationAction(ISD::MUL, {MVT::i32, MVT::i128}, Custom);
+ else
+ setOperationAction(ISD::MUL, MVT::i64, Custom);
- if (!Subtarget.hasStdExtM()) {
+ if (!Subtarget.hasStdExtM())
setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM},
XLenVT, Expand);
- } else {
- if (Subtarget.is64Bit()) {
- setOperationAction({ISD::SDIV, ISD::UDIV, ISD::UREM},
- {MVT::i8, MVT::i16, MVT::i32}, Custom);
- }
- }
+ else if (Subtarget.is64Bit())
+ setOperationAction({ISD::SDIV, ISD::UDIV, ISD::UREM},
+ {MVT::i8, MVT::i16, MVT::i32}, Custom);
setOperationAction(
{ISD::SDIVREM, ISD::UDIVREM, ISD::SMUL_LOHI, ISD::UMUL_LOHI}, XLenVT,
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