[PATCH] D151176: [RISCV] Custom lower fixed-length vector llvm.is.fpclass to vfclass.v

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll:11
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 768
----------------
The result of vfclass can only have single bit set according to the scalar documentation "Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags."  So it can never equal 768.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D151176/new/

https://reviews.llvm.org/D151176