[PATCH] D151176: [RISCV] Custom lower fixed-length vector llvm.is.fpclass to vfclass.v

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1045
+        // The instruction is only defined for SEW=16b and above.
+        if (VT.getVectorElementType() != MVT::i8) {
+          setOperationAction(ISD::IS_FPCLASS, VT, Custom);
----------------
Isn't VT an FP type here?


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4392
+
+  if (VT.isFixedLengthVector()) {
+    SDValue Op0 = Op.getOperand(0);
----------------
Why not scalable vectors?


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4408
+                           DAG.getUNDEF(ContainerDstVT), TDCMaskV, VL);
+    SDValue vmseq =
+        DAG.getNode(RISCVISD::SETCC_VL, DL, ContainerVT,
----------------
Capitalize variables names


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4410
+        DAG.getNode(RISCVISD::SETCC_VL, DL, ContainerVT,
+                    {ScalableOp0, TDCMaskV, DAG.getCondCode(ISD::SETEQ),
+                     DAG.getUNDEF(ContainerVT), Mask, VL});
----------------
Shouldn't we be emitting an AND and SETNE with 0 like the scalar code?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D151176/new/

https://reviews.llvm.org/D151176