[PATCH] D151177: [RISCV] Add i32 as a legal type for GPR register class.

[Craig Topper via Phabricator via llvm-commits]

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I'm investigating if it is feasible to have i32 as a legal type for RV64.
The first thing we need to do is make i32 a valid type for the GPR
register class.

Unfortunately, this disables a lot of type inferencing in tablegen
and requires us to explicitly add XLenVT to many isel patterns.

This might also allow us to get rid of the GPRF16/32/64 register class
from Zhinx/Zfinx/Zdinx by adding f16/f32/f64 to GPR type. Those classes
appear to only exist for type inference purposes today. In all other ways
they are identical to the GPR class.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151177

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoA.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td

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