[llvm] 4907649 - [RISCV] Fix some errors in the vector part of the scheduler model for SiFive7.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon May 22 12:46:34 PDT 2023
Author: Craig Topper
Date: 2023-05-22T12:46:25-07:00
New Revision: 490764985395c611720c30a2684ddaab485001ea
URL: https://github.com/llvm/llvm-project/commit/490764985395c611720c30a2684ddaab485001ea
DIFF: https://github.com/llvm/llvm-project/commit/490764985395c611720c30a2684ddaab485001ea.diff
LOG: [RISCV] Fix some errors in the vector part of the scheduler model for SiFive7.
-FP compare latency was too high.
-Compare instructions need to increase latency to assume no chaining
to later instructions.
vmv.x.s, vmv.s.x, vfmv.f.s, and vfmv.s.f aren't 8 cycles. From the
the perspective of the vector pipeline they are only 4 cycles. Though
vector to scalar has a much higher latency from the perspective
of the scalar pipeline. Will need to adjust in the future.
Reviewed By: michaelmaitland
Differential Revision: https://reviews.llvm.org/D151136
Added:
Modified:
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index dc833d0df755..2ddf3cc8224b 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -448,9 +448,6 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVShiftV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVShiftX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVShiftI", [SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICmpV", [SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICmpX", [SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICmpI", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMulV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMulX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFive7VA], mx, IsWorstCase>;
@@ -462,6 +459,12 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVIMovX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMovI", [SiFive7VA], mx, IsWorstCase>;
}
+ // Mask results can't chain.
+ let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVICmpV", [SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpX", [SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpI", [SiFive7VA], mx, IsWorstCase>;
+ }
}
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesOutputLMUL<mx>.c;
@@ -547,15 +550,20 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVFMulAddV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMulAddF", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFRecpV", [SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VA], mx, IsWorstCase>;
+ }
+ let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFSgnjV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFSgnjF", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFClassV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMergeV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMovV", [SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VA], mx, IsWorstCase>;
+ }
+ // Mask results can't chain.
+ let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFive7VA], mx, IsWorstCase>;
}
}
foreach mx = SchedMxListF in {
@@ -641,7 +649,7 @@ foreach mx = SchedMxList in {
}
// 16. Vector Permutation Instructions
-let Latency = 8, ResourceCycles = [1] in {
+let Latency = 4, ResourceCycles = [1] in {
def : WriteRes<WriteVIMovVX, [SiFive7VA]>;
def : WriteRes<WriteVIMovXV, [SiFive7VA]>;
def : WriteRes<WriteVFMovVF, [SiFive7VA]>;
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