[PATCH] D151139: [RISCV] Increase scalar integer divide latency for SiFive7.

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:201
 def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
-  let Latency = 16;
-  let ResourceCycles = [1, 15];
+  let Latency = 66;
+  let ResourceCycles = [1, 65];
----------------
>  1 bit per cycle so the worst case latency is the input width plus a couple cycles.

Why does latency take 2 extra cycles and resource cycles is only 1 extra cycle?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151139/new/

https://reviews.llvm.org/D151139