[PATCH] D151139: [RISCV] Increase scalar integer divide latency for SiFive7.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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The scalar divider produces 1 bit per cycle so the worst case
latency is the input width plus a couple cycles.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151139

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td


Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -198,12 +198,12 @@
 
 // Integer division
 def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
-  let Latency = 16;
-  let ResourceCycles = [1, 15];
+  let Latency = 66;
+  let ResourceCycles = [1, 65];
 }
 def : WriteRes<WriteIDiv32,  [SiFive7PipeB, SiFive7IDiv]> {
-  let Latency = 16;
-  let ResourceCycles = [1, 15];
+  let Latency = 34;
+  let ResourceCycles = [1, 33];
 }
 
 // Bitmanip


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