[PATCH] D150956: [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for ld1/ldnt1/st1/stnt1
Caroline via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 22 05:14:46 PDT 2023
CarolineConcatto accepted this revision.
CarolineConcatto added a comment.
This revision is now accepted and ready to land.
Probably because the test does not use any sve registers. So it can use the ones available.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D150956/new/
https://reviews.llvm.org/D150956
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