[PATCH] D150774: [AMDGPU] Simplify scavenging in indirectCopyToAGPR
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 22 03:55:42 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3c0d81d43fd7: [AMDGPU] Simplify scavenging in indirectCopyToAGPR (authored by foad).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D150774/new/
https://reviews.llvm.org/D150774
Files:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -634,11 +634,11 @@
assert(MBB.getParent()->getRegInfo().isReserved(Tmp) &&
"VGPR used for an intermediate copy should have been reserved.");
- // Only loop through if there are any free registers left, otherwise
- // scavenger may report a fatal error without emergency spill slot
- // or spill with the slot.
- while (RegNo-- && RS.FindUnusedReg(&AMDGPU::VGPR_32RegClass)) {
- Register Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
+ // Only loop through if there are any free registers left. We don't want to
+ // spill.
+ while (RegNo--) {
+ Register Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0,
+ /* AllowSpill */ false);
if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs)
break;
Tmp = Tmp2;
@@ -7919,9 +7919,10 @@
return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e32), DestReg);
// If available, prefer to use vcc.
- Register UnusedCarry = !RS.isRegUsed(AMDGPU::VCC)
- ? Register(RI.getVCC())
- : RS.scavengeRegister(RI.getBoolRC(), I, 0, false);
+ Register UnusedCarry =
+ !RS.isRegUsed(AMDGPU::VCC)
+ ? Register(RI.getVCC())
+ : RS.scavengeRegister(RI.getBoolRC(), I, 0, /* AllowSpill */ false);
// TODO: Users need to deal with this.
if (!UnusedCarry.isValid())
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