[PATCH] D150175: [X86] Fix instruction's ports info which is ported from SKL in AlderlakeP model

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


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Comment at: llvm/lib/Target/X86/X86SchedAlderlakeP.td:527
 }
-def : InstRW<[ADLPWriteResGroup2], (instregex "^JMP(16|32|64)m((_NT)?)$",
-                                              "^RET(16|32)$",
-                                              "^RORX(32|64)mi$")>;
+def : InstRW<[ADLPWriteResGroup2], (instregex "^RORX(32|64)mi$")>;
 def : InstRW<[ADLPWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
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Where are JMP and RET SchedWrite defined? Why the port change affect this code?


Repository:
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  https://reviews.llvm.org/D150175/new/

https://reviews.llvm.org/D150175