[PATCH] D150175: [X86] Fix instruction's ports info which is ported from SKL in AlderlakeP model

[Haohai, Wen via Phabricator via llvm-commits]

HaohaiWen added inline comments.


================
Comment at: llvm/lib/Target/X86/X86SchedAlderlakeP.td:527
 }
-def : InstRW<[ADLPWriteResGroup2], (instregex "^JMP(16|32|64)m((_NT)?)$",
-                                              "^RET(16|32)$",
-                                              "^RORX(32|64)mi$")>;
+def : InstRW<[ADLPWriteResGroup2], (instregex "^RORX(32|64)mi$")>;
 def : InstRW<[ADLPWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
----------------
LuoYuanke wrote:
> Where are JMP and RET SchedWrite defined? Why the port change affect this code?
Before this patch:
JMP with folded mem uses ADLPWriteResGroup2.

```
def ADLPWriteResGroup2 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
  let Latency = 6;
  let NumMicroOps = 2;
}
```

After this patch:
JMP uses default WriteJumpLd:

```
defm : ADLPWriteResPair<WriteJump, [ADLPPort00_06], 1, [1]>;
```

This multiclass defined WriteJumpLd as port = ADLPPort00_06 + ADLPPort02_03_11,  Lat = 1 + 5 = 6.
Same as previous one.

The reason why this code changed is some scheduling info of instructions ported from SKL use SKL store port (4) before this patch and is mapped to port(2,3,11) in this patch. This changes instructions group with same scheduling info thus the inferred code changed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150175/new/

https://reviews.llvm.org/D150175