[PATCH] D150175: [X86] Fix instruction's ports info which is ported from SKL in AlderlakeP model

[Haohai, Wen via Phabricator via llvm-commits]

HaohaiWen created this revision.
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AlderlakeP model is auto generated by D130897 <https://reviews.llvm.org/D130897> using scheduling data from:
(priority in dsc order):

1. Measured data in uops.info.
2. GoldenCove instruction throughput and latency in intel doc.
3. Existing SkylakeClientModel.

In step 3, some ports functionality has changed and new ports were
addedd from SKL to GLC so we need to map the port number. e.g.  Map uop
using port 4 (store) in SKL to port 4,9 in GLC.
The previous port mapping machanism in D130897 <https://reviews.llvm.org/D130897> didn't work and is fixed now.
Refresh this AlderlakeP model to update ports of instructions which
scheduling info are ported from SKL.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150175

Files:
  llvm/lib/Target/X86/X86SchedAlderlakeP.td
  llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
  llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
  llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x87.s
  llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-xsave.s

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