[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:292
+              MBBI->getOperand(1).getReg())
+          .addReg(MBBI->getOperand(1).getReg())
+          .addImm(4);
----------------
craig.topper wrote:
> Operand 1 isn't available to clobber here unless the kill flag is set. If's not set you would need to subtract the +4 after the store.
It's also possible that operand 1 is X0. I think that could occur for a global with an absolute address of 0x7fc.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149743/new/

https://reviews.llvm.org/D149743