[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:292
+              MBBI->getOperand(1).getReg())
+          .addReg(MBBI->getOperand(1).getReg())
+          .addImm(4);
----------------
craig.topper wrote:
> craig.topper wrote:
> > Operand 1 isn't available to clobber here unless the kill flag is set. If's not set you would need to subtract the +4 after the store.
> It's also possible that operand 1 is X0. I think that could occur for a global with an absolute address of 0x7fc.
def GPRNoX0 --- new register class without X0
```
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPF64:$rs2, GPR:$rs1, simm12:$imm12), []>;
```
to:
```
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPF64:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
```

Can this solve the problem?（I feel like I'm making the same mistake as the previous one.）


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D149743/new/

https://reviews.llvm.org/D149743