[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:274
+      .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
+      .addReg(MBBI->getOperand(1).getReg(), getKillRegState(0))
+      .add(MBBI->getOperand(2));
----------------
You don't need the getKillRegState call here. Also it's argument is a bool so passing 0 to it was questionable.


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Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:292
+              MBBI->getOperand(1).getReg())
+          .addReg(MBBI->getOperand(1).getReg())
+          .addImm(4);
----------------
Operand 1 isn't available to clobber here unless the kill flag is set. If's not set you would need to subtract the +4 after the store.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D149743/new/

https://reviews.llvm.org/D149743