[llvm] 913b95f - [RISCV] Add X1 as implicit def of cm.jalt.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-05-05T10:08:47-07:00
New Revision: 913b95fb80853894c479753f4f03a5efd3b0a5c8

URL: https://github.com/llvm/llvm-project/commit/913b95fb80853894c479753f4f03a5efd3b0a5c8
DIFF: https://github.com/llvm/llvm-project/commit/913b95fb80853894c479753f4f03a5efd3b0a5c8.diff

LOG: [RISCV] Add X1 as implicit def of cm.jalt.

This instruction updates the RA register.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D149933

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index 884d8bc9a955..962178b8a18e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -142,6 +142,7 @@ def CM_JT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm5:$index),
   let Inst{6-2} = index;
 }
 
+let Defs = [X1] in
 def CM_JALT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm8ge32:$index),
                          "cm.jalt", "$index">{
   bits<8> index;