[llvm] f9fa8a5 - [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

[Michael Maitland via llvm-commits]

Author: Michael Maitland
Date: 2023-05-05T10:16:35-07:00
New Revision: f9fa8a59970451ffd9ffc6b4c0554c7e7bd25ab0

URL: https://github.com/llvm/llvm-project/commit/f9fa8a59970451ffd9ffc6b4c0554c7e7bd25ab0
DIFF: https://github.com/llvm/llvm-project/commit/f9fa8a59970451ffd9ffc6b4c0554c7e7bd25ab0.diff

LOG: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

Based on the following description from Andrew W.

Instructions not mentioned here behave the same as integer ALU ops
rev8 only executes in the late-A and late-B ALUs
shNadd[.uw] only execute on the early-B and late-B ALUs
clz[w], ctz[w], and orc.b and all rotates only execute in the late-B ALU
pcnt[w] looks exactly like integer multiply
This patch does not account for early/late ALU in the model. It is coded based
on the pipes only.

Co-Authored-By: topperc <craig.topper at sifive.com>

Differential Revision: https://reviews.llvm.org/D149497

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 077b2d322a32..2328acb13a35 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -76,6 +76,35 @@ def : WriteRes<WriteIDiv32,  [SiFive7PipeB, SiFive7IDiv]> {
   let ResourceCycles = [1, 15];
 }
 
+// Bitmanip
+let Latency = 3 in {
+// Rotates are in the late-B ALU.
+def : WriteRes<WriteRotateImm, [SiFive7PipeB]>;
+def : WriteRes<WriteRotateImm32, [SiFive7PipeB]>;
+def : WriteRes<WriteRotateReg, [SiFive7PipeB]>;
+def : WriteRes<WriteRotateReg32, [SiFive7PipeB]>;
+
+// clz[w]/ctz[w] are in the late-B ALU.
+def : WriteRes<WriteCLZ, [SiFive7PipeB]>;
+def : WriteRes<WriteCLZ32, [SiFive7PipeB]>;
+def : WriteRes<WriteCTZ, [SiFive7PipeB]>;
+def : WriteRes<WriteCTZ32, [SiFive7PipeB]>;
+
+// cpop[w] look exactly like multiply.
+def : WriteRes<WriteCPOP, [SiFive7PipeB]>;
+def : WriteRes<WriteCPOP32, [SiFive7PipeB]>;
+
+// orc.b is in the late-B ALU.
+def : WriteRes<WriteORCB, [SiFive7PipeB]>;
+
+// rev8 is in the late-A and late-B ALUs.
+def : WriteRes<WriteREV8, [SiFive7PipeAB]>;
+
+// shNadd[.uw] is on the early-B and late-B ALUs.
+def : WriteRes<WriteSHXADD, [SiFive7PipeB]>;
+def : WriteRes<WriteSHXADD32, [SiFive7PipeB]>;
+}
+
 // Memory
 def : WriteRes<WriteSTB, [SiFive7PipeA]>;
 def : WriteRes<WriteSTH, [SiFive7PipeA]>;
@@ -279,11 +308,25 @@ def : ReadAdvance<ReadFClass64, 0>;
 
 def : ReadAdvance<ReadSFB, 0>;
 
+// Bitmanip
+def : ReadAdvance<ReadRotateImm, 0>;
+def : ReadAdvance<ReadRotateImm32, 0>;
+def : ReadAdvance<ReadRotateReg, 0>;
+def : ReadAdvance<ReadRotateReg32, 0>;
+def : ReadAdvance<ReadCLZ, 0>;
+def : ReadAdvance<ReadCLZ32, 0>;
+def : ReadAdvance<ReadCTZ, 0>;
+def : ReadAdvance<ReadCTZ32, 0>;
+def : ReadAdvance<ReadCPOP, 0>;
+def : ReadAdvance<ReadCPOP32, 0>;
+def : ReadAdvance<ReadORCB, 0>;
+def : ReadAdvance<ReadREV8, 0>;
+def : ReadAdvance<ReadSHXADD, 0>;
+def : ReadAdvance<ReadSHXADD32, 0>;
+
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
 defm : UnsupportedSchedV;
-defm : UnsupportedSchedZba;
-defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;