[llvm] 7b3b178 - [RISCV] Add DecoderNamespace to Zcmt instructions.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Fri May 5 10:08:56 PDT 2023


Author: Craig Topper
Date: 2023-05-05T10:08:43-07:00
New Revision: 7b3b178c825bfcf196685311bf33e4a5fa8ca8aa

URL: https://github.com/llvm/llvm-project/commit/7b3b178c825bfcf196685311bf33e4a5fa8ca8aa
DIFF: https://github.com/llvm/llvm-project/commit/7b3b178c825bfcf196685311bf33e4a5fa8ca8aa.diff

LOG: [RISCV] Add DecoderNamespace to Zcmt instructions.

The Zcmt instructions overlap encoding space with some C extension
instructions. Isolate to a separate namespace.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D149891

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 7c7aad05fa929..b5fc59ee9bacf 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -604,6 +604,14 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
     if (Result != MCDisassembler::Fail)
       return Result;
   }
+  if (STI.hasFeature(RISCV::FeatureStdExtZcmt)) {
+    LLVM_DEBUG(
+        dbgs() << "Trying Zcmt table (16-bit Table Jump Instructions):\n");
+    Result = decodeInstruction(DecoderTableRVZcmt16, MI, Insn, Address,
+                               this, STI);
+    if (Result != MCDisassembler::Fail)
+      return Result;
+  }
 
   LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
   // Calling the auto-generated decoder function.

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index 7d701883e4b5a..884d8bc9a9550 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -132,8 +132,8 @@ def C_SH : CStoreH_rri<0b100011, 0b1, "c.sh">,
            Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
 }
 
-let Predicates = [HasStdExtZcmt],
-hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt],
+    hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 def CM_JT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm5:$index),
                        "cm.jt", "$index">{
   bits<5> index;
@@ -149,7 +149,7 @@ def CM_JALT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm8ge32:$index),
   let Inst{12-10} = 0b000;
   let Inst{9-2} = index;
 }
-} // Predicates = [HasStdExtZcmt]
+} // DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt]...
 
 
 let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in{


        


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