[PATCH] D149034: [M68k] Add instruction selection support for zext with PCD addressing

[John Paul Adrian Glaubitz via Phabricator via llvm-commits]

glaubitz added a comment.

In D149034#4301169 <https://reviews.llvm.org/D149034#4301169>, @ids1024 wrote:

> Actually, after too much debugging, it looks like that error is an issue with `mul` when targeting the 68020. You can work around that by changing `setOperationAction(ISD::MUL, MVT::i32, Legal);` to `setOperationAction(ISD::MUL, MVT::i32, LibCall);`, but after that I still have a build error `LLVM ERROR: Cannot select: t42: ch = AtomicStore<(store unordered (s16) into %ir.30)> t40, t17, t38, src/mem/mod.rs:77:13`.
>
> So some more instruction selection fixes are needed for `mul` and `AtomicStore`.

Thanks a lot for debugging this. I had suspected MUL to be one of the problems, but I still lack some understanding on how LLVM IR works.

Maybe Sheng and Min can comment on this change and the other necessary fixes.


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  https://reviews.llvm.org/D149034/new/

https://reviews.llvm.org/D149034