[PATCH] D149034: [M68k] Add instruction selection support for zext with PCD addressing

[Ian D. Scott via Phabricator via llvm-commits]

ids1024 added a comment.

Actually, after too much debugging, it looks like that error is an issue with `mul` when targeting the 68020. You can work around that by changing `setOperationAction(ISD::MUL, MVT::i32, Legal);` to `setOperationAction(ISD::MUL, MVT::i32, LibCall);`, but after that I still have a build error `LLVM ERROR: Cannot select: t42: ch = AtomicStore<(store unordered (s16) into %ir.30)> t40, t17, t38, src/mem/mod.rs:77:13`.

So some more instruction selection fixes are needed for `mul` and `AtomicStore`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149034/new/

https://reviews.llvm.org/D149034