[PATCH] D149034: [M68k] Add instruction selection support for zext with PCD addressing

[Min-Yih Hsu via Phabricator via llvm-commits]

myhsu accepted this revision.
myhsu added a comment.
This revision is now accepted and ready to land.

LGTM Thanks!
Though could you update the patch description so that it's more descriptive? You can take a look at the commit message policy <https://llvm.org/docs/DeveloperPolicy.html#commit-messages>.

In D149034#4301169 <https://reviews.llvm.org/D149034#4301169>, @ids1024 wrote:

> Actually, after too much debugging, it looks like that error is an issue with `mul` when targeting the 68020. You can work around that by changing `setOperationAction(ISD::MUL, MVT::i32, Legal);` to `setOperationAction(ISD::MUL, MVT::i32, LibCall);`, but after that I still have a build error `LLVM ERROR: Cannot select: t42: ch = AtomicStore<(store unordered (s16) into %ir.30)> t40, t17, t38, src/mem/mod.rs:77:13`.
>
> So some more instruction selection fixes are needed for `mul` and `AtomicStore`.

I wouldn't lower 32-bit `MUL` to libcall when targeting >68020 since it already has native instructions for that size. For the AtomicStore issue it should be an easy fix: lower it to libcall same as AtomicLoad.


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