[PATCH] D149161: AMDGPU: Fix an assertion in SIOptimizeVGPRLiveRange
Ruiling, Song via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 25 20:24:44 PDT 2023
ruiling added a comment.
Why I cannot reproduce the assertion? I have tried on latest version and a version several days before.
================
Comment at: llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp:535
continue;
}
----------------
arsenm wrote:
> Could this see an undef subregister def? Should probably be assert !O.readsReg() (or maybe the loop is buggy to begin with by using use_operands?)
> Could this see an undef subregister def?
I guess not in SSA? or could you help point out what it would look like?
I think the undef use might also appear in blocks after `Endif`, so the assertion on part of the cases may be not quite helpful. As we already checked the register is not live in `Endif`, maybe we can just replace under the check `if (UseMI->isPHI() && UseBlock == Endif)`. But leaving some comment here still useful.
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https://reviews.llvm.org/D149161/new/
https://reviews.llvm.org/D149161
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