[PATCH] D148762: [RISCV] Rename some tablegen variables to improve code clarity in the vector load/store instruction definitions

[Nitin John Raj via Phabricator via llvm-commits]

nitinjohnraj updated this revision to Diff 515927.
nitinjohnraj added a comment.

Rebased


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148762/new/

https://reviews.llvm.org/D148762

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

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