[PATCH] D148762: [RISCV] Rename some tablegen variables to improve code clarity in the vector load/store instruction definitions
Nitin John Raj via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 21 15:40:38 PDT 2023
nitinjohnraj updated this revision to Diff 515941.
nitinjohnraj marked 2 inline comments as done.
nitinjohnraj added a comment.
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Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D148762/new/
https://reviews.llvm.org/D148762
Files:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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