[PATCH] D148523: [LegalizeTypes][VP] Widen fixed length vectors to VP nodes

Tue Apr 18 02:54:23 PDT 2023

luke added a comment.

In D148523#4277104 <https://reviews.llvm.org/D148523#4277104>, @frasercrmck wrote:

> In D148523#4274636 <https://reviews.llvm.org/D148523#4274636>, @craig.topper wrote:
>
>> Where do non-power of 2 vectors come from?
>
> Languages like SYCL, OpenCL, and shader languages certainly provide vectors of length 3 (which are usually sized as 4 for allocations and such). I've never seen vector lengths other than 3 in the real world.

The two cases I had in mind:

1. If the vector interleave/deinterleave intrinsics are extended to support interleave groups > 2, the loop vectorizer can emit non-power of 2 vectors loads/stores, e.g. 3 groups and a VF of 4 would result in a 12-element load
2. It might be interesting to explore loosening the restriction on SLP that it must vectorise bundles by powers of 2.

Neither of these actually exist in main yet though. I thought it would be interesting to submit this patch anyway as a proof of concept, and am happy to wait until we have some concrete use cases for it.

> I've had a long-standing task in my backlog to see if we can make those 3-element vectors legal in the RISC-V backend for better code.

Credit where credit is due, the basis of this patch came from your comment about fixed-length vectors in https://reviews.llvm.org/D111248!

Do you still remember where were the regressions you saw?
I can confirm that vp_load/vp_store are at least missing one optimisation, in `insertelt_v3i64` in `fixed-vectors-insert.ll`. I'm not sure if it's as a result of not scalarizing or because DAGCombiner doesn't have enough aliasing information.

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