[PATCH] D148523: [LegalizeTypes][VP] Widen fixed length vectors to VP nodes

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

In D148523#4274636 <https://reviews.llvm.org/D148523#4274636>, @craig.topper wrote:

> Where do non-power of 2 vectors come from?

Languages like SYCL, OpenCL, and shader languages certainly provide vectors of length 3 (which are usually sized as 4 for allocations and such). I've never seen vector lengths other than 3 in the real world.

I've had a long-standing task in my backlog to see if we can make those 3-element vectors legal in the RISC-V backend for better code.  For that reason, I find this patch quite elegant.

I don't know if we want a target override to control this behaviour on top of the legality of the VP operations themselves. Just in case a target has legal VP nodes but prefers the widening for whatever reason. I'd suggest we keep this approach as-is, and let other targets tweak the behaviour if it's not suitable.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148523/new/

https://reviews.llvm.org/D148523