[PATCH] D148229: [DAGCombine][AArch64][CodeGen] Allow tranformable vectors to a legal for MULH lowering and use SVE's MULH for fixed vector types.

Mon Apr 17 08:27:42 PDT 2023

dmgreen added inline comments.

================
Comment at: llvm/test/CodeGen/Thumb2/mve-vmulh.ll:77
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmullb.s16 q0, q0, q1
-; CHECK-NEXT:    vshr.s32 q0, q0, #16
+; CHECK-NEXT:    vmovlb.s16 q1, q1
+; CHECK-NEXT:    vmovlb.s16 q0, q0
----------------
This still looks wrong I'm afraid (and worse).

See https://reviews.llvm.org/D119075 (and https://reviews.llvm.org/D119556) for how I once thought of doing this with custom legalization from the target. That didn't get through review though, and we worked around it for some hadd/abd by using no wrap flags.

My understanding is that it will need to use the original type size for the mulh, otherwise the shift will be incorrect. You might be able to replace the NVCAST with bitcast providing it doesn't go incorrectly for big endian. I'm not sure all targets would like that though.

================
Comment at: llvm/test/CodeGen/Thumb2/mve-vmulh.ll:94
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmullb.u16 q0, q0, q1
-; CHECK-NEXT:    vshr.u32 q0, q0, #16
+; CHECK-NEXT:    vmov.i32 q0, #0x0
 ; CHECK-NEXT:    bx lr
----------------
This is just returning 0.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148229/new/

https://reviews.llvm.org/D148229