[PATCH] D148229: [DAGCombine][AArch64][CodeGen] Allow tranformable vectors to a legal for MULH lowering and use SVE's MULH for fixed vector types.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll:98
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
+; CHECK-NEXT:    smulh z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    and z0.s, z0.s, #0xffff
----------------
sdesmalen wrote:
> This doesn't seem right because this instruction is sign-extending i32 elements, not the i16 elements that are passed in as the arguments.
> 
> I would have expected `smulh z0.h, p0/m, z0.h, z1.h` instead.
I still don't think this is correct, because it's not keeping the correct part of the result. I think the promotion could work by shifting the operands to the left by 16bits, doing the smulh on 32-bit elements, and then shifting the result right again by 16bits. But this is probably less efficient than the original code (sign-extend + mul + shift-right), so it seems better to avoid combining this case entirely and in the DAGCombine just add a check that the transformed type's element type is the same as the element type of NarrowVT (otherwise that would imply the need for type promotion)


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  https://reviews.llvm.org/D148229/new/

https://reviews.llvm.org/D148229