[PATCH] D148229: [DAGCombine][AArch64][CodeGen] Allow tranformable vectors to a legal for MULH lowering and use SVE's MULH for fixed vector types.

[Dinar Temirbulatov via Phabricator via llvm-commits]

dtemirbulatov added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9921
+  // rely on legalization to split/combine the result.
+  if (NarrowVT.isVector()) {
+    EVT TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), NarrowVT);
----------------
sdesmalen wrote:
> this check is now irrelevant, you can remove the if/else entirely.
Hmm, I have got several errors on scalar handling of MULH on RISCV and LoongArch targets without isVector() check.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148229/new/

https://reviews.llvm.org/D148229