[PATCH] D148185: Add more efficient bitwise vector reductions on AArch64

[Markus Everling via Phabricator via llvm-commits]

Sp00ph added a comment.

In D148185#4268948 <https://reviews.llvm.org/D148185#4268948>, @dmgreen wrote:

> Is it worth splitting this into i1 and non-i1 parts? There are quite a few changes in the test.

I'm pretty sure removing the i1 optimization would lead to even more test cases being changed, as codegen currently already does the i1 optimization (presumably in some platform independent lowering of `REDUCE_{AND,OR}`. I introduced that i1 optimization mainly to keep the i1 vector reductions from regressing.


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https://reviews.llvm.org/D148185