[PATCH] D148185: Add more efficient bitwise vector reductions on AArch64

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13248
+
+    // Iteratively apply the bitwise operator to the first and second half
+    // of the vector until only one element remains.
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dmgreen wrote:
> Would it be possible for vector <= 64bits to use the 64bit type sizes? It won't matter in a lot of cases but some cpu's have a higher throughput for 64bit vectors.
For <=64 bits, don't you want to switch to integer registers?  `orr x0, x0, x0, lsr #32` etc. is generally going to be faster than dup+orr.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148185/new/

https://reviews.llvm.org/D148185