[PATCH] D148185: Add more efficient bitwise vector reductions on AArch64

[Markus Everling via Phabricator via llvm-commits]

Sp00ph updated this revision to Diff 513813.
Sp00ph added a comment.

Changes the codegen to split the vectors until they're at most 64 bits large and then do the remaining work in an integer register. This reduces instruction count in many cases, as codegen is able to combine the shift and bitwise operation into one instruction. Also revert to using `andv/orv/eorv` if SVE is available.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148185/new/

https://reviews.llvm.org/D148185

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
  llvm/test/CodeGen/AArch64/double_reduct.ll
  llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
  llvm/test/CodeGen/AArch64/reduce-and.ll
  llvm/test/CodeGen/AArch64/reduce-or.ll
  llvm/test/CodeGen/AArch64/reduce-xor.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-bool.ll
  llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

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