[PATCH] D148229: [DAGCombine][AArch64][CodeGen] Allow 2x bigger vectors than legal for mulh lowering and use SVE's mulh for fixed vector types.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9924
+        !TLI.isOperationLegalOrCustom(
+            MulhOpcode, NarrowVT.getHalfNumVectorElementsVT(*DAG.getContext())))
+      return SDValue();
----------------
if there any chance that odd element count vectors can get here?


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll:16
 ; Don't use SVE for 64-bit vectors.
 ; FIXME: The codegen for the >=256 bits case can be improved.
 define <8 x i8> @smulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {
----------------
remove the FIXME?


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll:151
 ; Don't use SVE for 64-bit vectors.
 ; FIXME: The codegen for the >=256 bits case can be improved.
 define <4 x i16> @smulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 {
----------------
FIXME?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148229/new/

https://reviews.llvm.org/D148229