[PATCH] D147096: AMDGPU: Created a sub-register class for the return address operand in the tail call return instruction

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:822
+// return address only.
+def CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, (add (trunc SGPR_64, 16))> {
+  let CopyCost = SGPR_64.CopyCost;
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foad wrote:
> Doesn't this depend on the calling convention? CSR_AMDGPU_SGPRs and CSR_AMDGPU_SI_Gfx_SGPRs are different.
Yeah, the amdgpu_gfx calling convention has s[32:63] as scratch registers, so picking a register out of s[0:32] as return register makes tail calls with the amdgpu_gfx calling convention impossible.


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  https://reviews.llvm.org/D147096/new/

https://reviews.llvm.org/D147096