[PATCH] D147096: AMDGPU: Created a sub-register class for the return address operand in the tail call return instruction

[Changpeng Fang via Phabricator via llvm-commits]

cfang added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:822
+// return address only.
+def CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, (add (trunc SGPR_64, 16))> {
+  let CopyCost = SGPR_64.CopyCost;
----------------
sebastian-ne wrote:
> foad wrote:
> > Doesn't this depend on the calling convention? CSR_AMDGPU_SGPRs and CSR_AMDGPU_SI_Gfx_SGPRs are different.
> Yeah, the amdgpu_gfx calling convention has s[32:63] as scratch registers, so picking a register out of s[0:32] as return register makes tail calls with the amdgpu_gfx calling convention impossible.
We are seeing a tail call return address in callee saved registers, which were over-written during restore of the CSR before return. This is a correct issue. To solve this, we think it is better to restrict the tail call return address to be in the scratch registers, rather than in sreg_64 which could be a CSR. 
   I am not sure whether the same issue exists with amdgpu_gfx calling convention. If yes, we may need to do similar thing to restrict to scratch register for tail call return address.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147096/new/

https://reviews.llvm.org/D147096