[PATCH] D147096: AMDGPU: Created a sub-register class for the return address operand in the tail call return instruction

Tue Apr 11 04:43:36 PDT 2023

arsenm added inline comments.

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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:2490
+  if (!B.getMRI()->getRegClassOrNull(PCReg))
+    B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass);

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cfang wrote:
> arsenm wrote:
> > cdevadas wrote:
> > > Not sure this is the right thing to do. @foad can you review this?
> > Looking at the test diffs, I think we should introduce a copy to the correct register class when TCRETURN is inserted. If the G_GLOBAL_VALUE has other uses, it's over constrained
> I would say the test diff you saw is from different places even though here we may have the same issue. I plan to commit as it is for now.
> and continue to investigate the performance issue related to the regClass change. Thanks.
Using constrainOperandRegClass should work 

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147096/new/

https://reviews.llvm.org/D147096