[PATCH] D141247: [GlobalISelEmitter] handle operand without MVT/class

ChenZheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Apr 9 21:50:56 PDT 2023 

shchenz updated this revision to Diff 512067.
shchenz retitled this revision from "[GlobalISelEmitter][WIP] handle operand without MVT/class" to "[GlobalISelEmitter] handle operand without MVT/class".
shchenz edited the summary of this revision.
shchenz added a comment.

Change this to formal review


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141247/new/

https://reviews.llvm.org/D141247

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/AArch64/arm64-vcvt.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
  llvm/test/CodeGen/AMDGPU/constrained-shift.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
  llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
  llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
  llvm/test/CodeGen/AMDGPU/roundeven.ll
  llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
  llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
  llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
  llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td
  llvm/utils/TableGen/GlobalISelEmitter.cpp

More information about the llvm-commits mailing list