[PATCH] D144530: [RISCV] MC layer support for SiFive VCIX vendor extension.

[Brandon Wu via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0b9a620b832e: [RISCV] Support assembler and dis-assembler for VCIX extension. (authored by Nelson1225, committed by 4vtomat).

Changed prior to commit:
  https://reviews.llvm.org/D144530?vs=506292&id=512063#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144530/new/

https://reviews.llvm.org/D144530

Files:
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/xsfvcp-invalid.s
  llvm/test/MC/RISCV/rvv/xsfvcp.s

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