[PATCH] D147609: [RISCV] Use non-strided load if VL=1 for optimized zero stride loads

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 511351.
luke added a comment.

Simplify IsStrided


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147609/new/

https://reviews.llvm.org/D147609

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

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