[PATCH] D147609: [RISCV] Use non-strided load if VL=1 for optimized zero stride loads
Luke Lau via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 6 03:22:23 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5f2145adf9e3: [RISCV] Use non-strided load if VL=1 for optimized zero stride loads (authored by luke).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D147609/new/
https://reviews.llvm.org/D147609
Files:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
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