[PATCH] D147609: [RISCV] Use non-strided load if VL=1 for optimized zero stride loads

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2088
 
-    SDValue Operands[] = {Ld->getBasePtr(),
-                          CurDAG->getRegister(RISCV::X0, XLenVT), VL, SEW,
-                          Ld->getChain()};
+    bool IsStrided = true;
+    // If VL=1, then we don't need to do a strided load and can just do a
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Does this simplify to `bool IsStrided = !isOneConstant(VL)`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147609/new/

https://reviews.llvm.org/D147609