[PATCH] D147609: [RISCV] Use non-strided load if VL=1 for optimized zero stride loads

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2076-2081
     if (IsScalarMove) {
       // We could deal with more VL if we update the VSETVLI insert pass to
       // avoid introducing more VSETVLI.
       if (!isOneConstant(Node->getOperand(2)))
         break;
       selectVLOp(Node->getOperand(2), VL);
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Could `VM_S_X_VL` nodes be lowered to non-strided loads with VL=1? Since only the first lane needs to be written to. 


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  https://reviews.llvm.org/D147609/new/

https://reviews.llvm.org/D147609