[PATCH] D146735: [CodeGen] Don't include aliases in RegisterClassInfo::IgnoreCSRForAllocOrder

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: qcolombet, MatzeB, Srividya-Karumuri.
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Previously we called ignoreCSRForAllocationOrder on every alias of every
CSR which was expensive on targets like AMDGPU which define a very large
number of overlapping register tuples.

No functional change intended, but I can't verify that because this code
does not appear to be used by any in-tree targets anyway.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146735

Files:
  llvm/lib/CodeGen/RegisterClassInfo.cpp


Index: llvm/lib/CodeGen/RegisterClassInfo.cpp
===================================================================
--- llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -94,8 +94,7 @@
   // if ignoreCSRForAllocationOrder is evaluated differently.
   BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
   for (const MCPhysReg *I = CSR; *I; ++I)
-    for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
-      CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
+    CSRHintsForAllocOrder[*I] = STI.ignoreCSRForAllocationOrder(mf, *I);
   if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
       IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
     Update = true;


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