[PATCH] D146635: [LegalizeTypes][RISCV] Add a special case for (add X, -1) to ExpandIntRes_ADDSUB

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:3043
+    if (isAllOnesConstant(LoOps[1]))
+      Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps[0], Carry);
+    else
----------------
This overwrites the `Hi` that was calculated above and is only correct if HiOps[1] is also all ones.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146635/new/

https://reviews.llvm.org/D146635