[PATCH] D146635: [LegalizeTypes][RISCV] Add a special case for (add X, -1) to ExpandIntRes_ADDSUB

[Liao Chunyu via Phabricator via llvm-commits]

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On targets without ADDCARRY or ADDE, we need to emit a separate
 SETCC to determine carry from the low half to the high half. 
 The high half is calculated by a series of ADDs.

Without this patch, we get:

  Hi = (add (add LHSHi,(setult Lo, LHSLo), -1)

Where as with the patch we get:

  Hi = (sub LHSHi, (seteq LHSLo, 0)) 
   

Similar to gcc: https://godbolt.org/z/Kb78r4zh6


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146635

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
  llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
  llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

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