[PATCH] D146635: [LegalizeTypes][RISCV] Add a special case for (add X, -1) to ExpandIntRes_ADDSUB

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy updated this revision to Diff 507738.
liaolucy edited the summary of this revision.
liaolucy added a comment.

Address comment. 
Add Only RHSLo is -1 we can instead do (setne Lo, 0) and more testcases, like gcc: https://godbolt.org/z/M83f6rz39


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146635/new/

https://reviews.llvm.org/D146635

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/RISCV/alu64.ll
  llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
  llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
  llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

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