[PATCH] D146050: [RISCV]Combine (select(seteq (and X, 1 << C), 0) to select_cc

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10656
+                         N->getOperand(2) /*FalseV*/, CondV->getOperand(2)};
+        return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), Ops);
+      }
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This looks like we're using ISD::SELECT_CC to hide from other transforms. We don't normally use ISD::SELECT_CC on RISC-V. Can we detect the srl form as an additional case in translateSetCCForBranch instead?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D146050/new/

https://reviews.llvm.org/D146050