[PATCH] D146050: [RISCV]Combine (select(seteq (and X, 1 << C), 0) to select_cc

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10656
+                         N->getOperand(2) /*FalseV*/, CondV->getOperand(2)};
+        return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), Ops);
+      }
----------------
craig.topper wrote:
> This looks like we're using ISD::SELECT_CC to hide from other transforms. We don't normally use ISD::SELECT_CC on RISC-V. Can we detect the srl form as an additional case in translateSetCCForBranch instead?
```
Optimized type-legalized selection DAG: %bb.0 'bit_31_nz_select_i32:'
SelectionDAG has 13 nodes:
  t0: ch,glue = EntryToken
        t2: i32,ch = CopyFromReg t0, Register:i32 %0
      t21: i32 = srl t2, Constant:i32<31>
      t4: i32,ch = CopyFromReg t0, Register:i32 %1
      t6: i32,ch = CopyFromReg t0, Register:i32 %2
    t12: i32 = select t21, t4, t6
  t14: ch,glue = CopyToReg t0, Register:i32 $x10, t12
  t15: ch = RISCVISD::RET_FLAG t14, Register:i32 $x10, t14:1
```


The test is not executed by translateSetCCForBranch. It is returned earlier in lowerSELECT.

```
  // If the condition is not an integer SETCC which operates on XLenVT, we need
  // to emit a RISCVISD::SELECT_CC comparing the condition to zero. i.e.:
  // (select condv, truev, falsev)
  // -> (riscvisd::select_cc condv, zero, setne, truev, falsev)
  if (CondV.getOpcode() != ISD::SETCC ||
      CondV.getOperand(0).getSimpleValueType() != XLenVT) {
    SDValue Zero = DAG.getConstant(0, DL, XLenVT);
    SDValue SetNE = DAG.getCondCode(ISD::SETNE);

    SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};

    return DAG.getNode(RISCVISD::SELECT_CC, DL, VT, Ops);
  }
```

Maybe the code for LowerSelect needs to be refactored, I'll try it.



Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D146050/new/

https://reviews.llvm.org/D146050