[PATCH] D145551: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode

[lizhijin via Phabricator via llvm-commits]

lizhijin marked an inline comment as done.
lizhijin added a comment.

ping



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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:5882
+
+  def : SVE_2_Op_Imm_Pat_Zero<nxv16i8, op, nxv16i1, i32, SVEShiftImmL8, !cast<Pseudo>(NAME # _ZERO_B)>;
+  def : SVE_2_Op_Imm_Pat_Zero<nxv8i16, op, nxv8i1,  i32, SVEShiftImmL16, !cast<Pseudo>(NAME # _ZERO_H)>;
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paulwalker-arm wrote:
> These operand types (plus the tvecshiftL ones above) are specific to left shifts.  You might want to take inspiration from `sve_int_shift_pred_bhsd`.
Updated. Thanks!


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