[PATCH] D145551: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode

[Allen zhong via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG22c3ba4bb519: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode (authored by lizhijin, committed by Allen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145551/new/

https://reviews.llvm.org/D145551

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm-zero.ll

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